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lt3975 1 3975f typical application features description 42v, 2.5a, 2mhz step-down switching regulator with 2.7a quiescent current the lt ? 3975 is an adjustable frequency monolithic buck switching regulator that accepts a wide input voltage range up to 42v. low quiescent current design consumes only 2.7a of supply current while regulating with no load. low ripple burst mode operation maintains high efficiency at low output currents while keeping the output ripple below 15mv in a typical application. the lt3975 can supply up to 2.5a of load current and has current limit foldback to limit power dissipation during short circuit. a low dropout voltage of 500mv is maintained when the input voltage drops below the programmed output voltage, such as during automotive cold crank. an internally compensated current mode topology is used for fast transient response and good loop stability. a high efficiency 75m switch is included on the die along with a boost schottky diode and the necessary oscillator, control, and logic circuitry. an accurate 1.02v threshold enable pin can be driven directly from a microcontroller or used as a programmable undervoltage lockout. a capacitor on the ss pin provides a controlled inrush current (soft-start). a power good flag signals when v out reaches 91.6% of the programmed output voltage. the lt3975 is available in a small 16-lead msop package with exposed pad for low thermal resistance. no-load supply current 3.3v step-down converter applications n ultralow quiescent current: 2.7a i q at 12v in to 3.3v out n low ripple burst mode ? operation output ripple < 15mv p-p n wide input range: operation from 4.3v to 42v n 2.5a maximum output current n excellent start-up and dropout performance n adjustable switching frequency: 200khz to 2mhz n synchronizable between 250khz to 2mhz n accurate programmable undervoltage lockout n low shutdown current: i q = 700na n power good flag n soft-start capability n thermal shutdown protection n current limit foldback with soft-start override n saturating switch design: 75m on resistance n small, thermally enhanced 16-lead msop package n automotive battery regulation n portable products n industrial supplies l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. v in en boost off on v in 4.3v to 42v pg 0.47f pds560 47f 1210 3975 ta01a 10nf 10f 576k f = 600khz 78.7k v out 3.3v 2.5a 3.3h lt3975 ss rt sw out fb sync gnd 1m 10pf input voltage (v) 0 1.0 input current (a) 1.5 2.5 3.0 3.5 4.5 5 25 35 3975 ta01b 2.0 4.0 20 45 10 15 30 in regulation 40
lt3975 2 3975f absolute maximum ratings v in , en voltage (note 3) ........................................... 42v boost pin voltage ................................................... 55v boost pin above sw pin ......................................... 30v fb, rt, sync, ss voltage ........................................... 6v pg voltage ................................................................ 30v out voltage .............................................................. 16v operating junction temperature range (note 2) lt3975e ............................................. C40c to 125c lt3975i .............................................. C40c to 125c lt3975h ............................................ C40c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c (note 1) 1 2 3 4 5 6 7 8 fb ss out boost sw sw sw nc 16 15 14 13 12 11 10 9 sync pg rt en v in v in v in nc top view 17 gnd mse package 16-lead plastic msop ja = 40c/w exposed pad (pin 17) is gnd, must be soldered to pcb pin configuration the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) order information lead free finish tape and reel part marking* package description temperature range lt3975emse#pbf lt3975emse#trpbf 3975 16-lead plastic msop C40c to 125c lt3975imse#pbf lt3975imse#trpbf 3975 16-lead plastic msop C40c to 125c lt3975hmse#pbf lt3975hmse#trpbf 3975 16-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units minimum input voltage (note 3) l 4 4.3 v dropout comparator threshold (v in C out) falling 430 500 570 mv dropout comparator threshold hysteresis 25 mv quiescent current from v in v en low v en high, v sync low v en high, v sync low l 0.7 1.6 1.3 2.7 30 a a a fb pin current v fb = 1.5v l 0.1 12 na feedback voltage l 1.183 1.173 1.197 1.197 1.212 1.222 v v fb voltage line regulation 4.3v < v in < 40v (note 3) 0.0003 0.01 %/v switching frequency r t = 11.8k r t = 41.2k r t = 294k 1.8 0.8 160 2.25 1 200 2.7 1.2 240 mhz mhz khz minimum switch on-time 105 ns minimum switch off-time (note 4) 150 200 ns electrical characteristics
lt3975 3 3975f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3975e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the lt3975i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3975h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: minimum input voltage depends on application circuit. note 4: the lt3975 contains circuitry that extends the maximum duty cycle if there is sufficient voltage across the boost capacitor. see the application information section for more details. note 5: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the switch. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. parameter conditions min typ max units switch current limit v fb = 1v 4 5.4 6.8 a foldback switch current limit v fb = 0v 3.3 a switch v cesat i sw = 1a 80 mv switch leakage current 0.02 1 a boost schottky forward voltage i sh = 100ma 730 mv boost schottky reverse leakage v reverse = 12v 0.02 2 a minimum boost voltage (note 5) l 1.3 1.8 v boost pin current i sw = 1a, v boost C v sw = 3v 20 32 ma en voltage threshold en falling, v in 4.3v l 0.92 1.02 1.12 v en voltage hysteresis 60 mv en pin current 0.2 20 na pg threshold offset from v fb v fb falling 5 8.4 13 % pg hysteresis as % of output voltage 1.7 % pg leakage v pg = 3v 0.02 1 a pg sink current v pg = 0.4v l 125 480 a sync low threshold 0.6 1.0 v sync high threshold 1.18 1.5 v sync pin current v sync = 6v 0.1 na ss source current v ss = 0.5v 0.9 1.8 2.6 a
lt3975 4 3975f typical performance characteristics efficiency at 3.3v out no-load supply current no-load supply current reference voltage load regulation line regulation efficiency at 5v out efficiency at 3.3v out efficiency at 5v out t a = 25c, unless otherwise noted. load current (a) 0 efficiency (%) 80 90 100 2 3975 g01 70 60 75 85 95 65 55 50 0.5 1 1.5 2.5 12v 24v 36v f sw = 800khz v out = 5v l = mss1260-332nl load current (a) 0 efficiency (%) 70 80 90 2 3975 g02 60 50 65 75 85 55 45 40 0.5 1 1.5 2.5 12v 24v 36v front page application v out = 3.3v l = mss1260-332nl load current (ma) 0.01 0 efficiency (%) 20 40 60 0.1 1 10 100 3975 g03 1000 80 100 10 30 50 70 90 10000 12v 24v 36v f sw = 800khz v out = 5v l = mss1260-332nl load current (ma) 0.01 0 efficiency (%) 20 40 60 0.1 1 10 100 3975 g03 1000 80 10 30 50 70 90 10000 12v 24v 36v front page application v out = 3.3v l = mss1260-332nl input voltage (v) 0 1.0 input current (a) 1.5 2.5 3.0 3.5 4.5 5 25 35 3975 g05 2.0 4.0 20 45 10 15 30 in regulation v out = 3.3v 40 temperature (c) 10 input current (a) 1000 10000 ?55 65 125 3975 g06 1 5?25 95 155 35 100 front page application v in = 12v v out = 3.3v due to catch diode leakage temperature (c) ?55 reference voltage (v) 1.190 1.220 1.225 1.230 5 65 95 3975 g07 1.180 1.175 1.210 1.200 1.185 1.215 1.170 1.205 1.195 ?25 35 125 155 input voltage (v) 0 change in v out (%) ?0.05 0 0.05 1.5 2.5 3975 g08 ?0.10 ?0.15 ?0.20 0.5 1 2 0.10 0.15 0.20 v in = 12v v out = 5v input voltage (v) 5 ?0.05 change in v out (%) ?0.04 ?0.02 ?0.01 0 0.05 0.02 15 25 30 45 2975 g09 ?0.03 0.03 0.04 0.01 10 20 35 40 v out = 5v load = 1a
lt3975 5 3975f typical performance characteristics current limit foldback soft-start switch v cesat boost pin current minimum on-time minimum off-time thermal derating switch current limit switch current limit t a = 25c, unless otherwise noted. switch current (a) 0 0 v cesat (mv) 50 100 150 200 250 0.5 1 1.5 2.0 3975 g15 2.5 3.0 switch current (a) 0 0 boost pin current (ma) 10 20 30 0.5 1 1.5 2 3975 g16 2.5 40 50 5 15 25 35 45 3 temperature (c) ?50 0 load current (a) 0.5 1.0 1.5 2.0 0 50 100 150 3975 g10 2.5 3.0 ?25 25 75 125 i-grade h-grade v in = 12v v out = 5v limited by maximum junction temperature ja = 40c/w duty cycle 0 5 6 7 0.8 3975 g11 4 3 0.2 0.4 0.6 1 2 1 0 current limit (a) temperature (c) ?55 current limit (a) 6.5 35 3975 g12 5.0 4.0 ?25 5 65 3.5 3.0 7.0 6.0 5.5 4.5 95 125 155 30% duty cycle fb pin voltage (v) 0 0 current limit (a) 1 2 3 4 6 0.2 0.4 0.6 0.8 3975 g13 1.0 1.2 5 30% duty cycle v ss = 3v ss pin voltage (v) 0 0 current limit (a) 1 2 3 4 5 6 0.5 1 1.5 2 3975 g14 2.5 v fb = 1v v fb = 0v 30% duty cycle temperature (c) ?55 minimum on-time (ns) 100 160 170 180 5 65 95 3975 g17 80 140 120 90 150 60 70 130 110 ?25 35 125 155 v sync = 0v f sw = 2mhz load = 1a load = 2.5a temperature (c) ?55 100 minimum off-time (ns) 110 130 140 150 200 170 5 65 95 125 3975 g18 120 180 190 160 ?25 35 155 v sync = 0v f sw = 2mhz load = 1a load = 2.5a
lt3975 6 3975f typical performance characteristics internal undervoltage lockout (uvlo) en thresholds pg thresholds minimum input voltage, v out = 5v minimum input voltage, v out = 3.3v burst frequency switching frequency r t programmed switching frequency frequency foldback t a = 25c, unless otherwise noted. temperature (c) ?55 switching frequency (khz) 660 720 780 35 95 3975 g19 600 540 ?25 5 65 125 155 480 420 switching frequency (mhz) 0.2 0 r t resistor (k) 50 150 200 250 350 0.4 1.2 1.6 3975 g20 100 300 1 2 2.2 0.6 0.8 1.4 1.8 fb pin voltage (v) 0 700 600 500 400 300 200 100 0 0.6 1 3975 g21 0.2 0.4 0.8 1.2 switching frequency (khz) temperature (c) ?55 input voltage (v) 4 5 6 35 95 3975 g22 3 2 ?25 5 65 125 155 1 0 temperature (c) ?55 en threshold (v) 1.08 35 3975 g23 1.05 1.03 ?25 5 65 1.02 1.01 1.09 1.07 1.06 1.04 95 125 155 en rising en falling temperature (c) ?55 pg threshold (v) 1.11 35 3975 g24 1.08 1.06 ?25 5 65 1.05 1.04 1.12 1.10 1.09 1.07 95 125 155 fb rising fb falling load current (a) 0 input voltage (v) 5.5 6.0 6.5 2 3975 g25 5.0 4.5 4.0 0.5 1 1.5 2.5 v out = 5v f sw = 800khz to run/to start load current (a) 0 input voltage (v) 4.0 4.5 5.0 2 3975 g26 3.5 3.0 2.5 0.5 1 1.5 2.5 v out = 3.3v front page application to run/to start load current (ma) 0 switching frequency (khz) 500 600 700 160 3975 g27 400 300 0 40 80 120 20 60 100 140 200 100 900 800 v out = 5v f sw = 800khz v out = 3.3v f sw = 600khz
lt3975 7 3975f ss pin current typical performance characteristics start-up/dropout performance start-up/dropout performance boost capacitor charger boost diode forward voltage dropout comparator thresholds burst mode switching waveforms dropout switching waveforms full frequency switching waveforms t a = 25c, unless otherwise noted. temperature (c) ?55 ss pin current (a) 2.4 35 3975 g28 1.8 1.4 ?25 5 65 1.2 1.0 2.6 2.2 2.0 1.6 95 125 155 v ss = 0.5v out pin voltage (v) 0 out pin current (ma) 80 120 16 3975 g29 40 0 4 8 12 2 6 10 14 160 60 100 20 140 v bst = v in boost diode current (a) 0 boost diode voltage (v) 0.8 1.0 1.2 2 3975 g30 0.6 0.4 0 0.5 1 1.5 0.2 1.6 1.4 temperature (c) ?55 400 dropout threshold (mv) 420 460 480 500 600 540 5 65 95 125 3975 g31 440 560 580 520 ?25 35 155 v out rising v out falling v in 1v/div v out 1v/div v out v in 100ms/div 2.5 load (2a in regulation) 3975 g32 v in 1v/div v out 1v/div v out v in 100ms/div 1k load (5ma in regulation) 3975 g33 v sw 5v/div v out 10mv/div i l 0.5a/div 5s/div v in = 12v v out = 3.3v i load = 20ma c out = 47f 3975 g34 v sw 5v/div v out 20mv/div i l 1a/div 1s/div v in = 12v v out = 3.3v i load = 1a c out = 47f 3975 g35 v sw 2v/div v out 50mv/div i l 1a/div 5s/div v in = 5v v out set for 5v i load = 0.5a c out = 47f 3975 g36
lt3975 8 3975f pin functions fb (pin 1): the lt3975 regulates the fb pin to 1.197v. connect the feedback resistor divider tap to this pin. also, connect a phase lead capacitor between fb and the output. typically, this capacitor is 10pf. ss (pin 2): a capacitor is tied between ss and ground to slowly ramp up the peak current limit of the lt3975 on start-up. there is an internal 1.8a pull-up on this pin. the soft-start capacitor is actively discharged when the en pin goes low, during undervoltage lockout or thermal shutdown. float this pin to disable soft-start. out (pin 3): this pin is an input to the dropout comparator which maintains a minimum dropout of 500mv between v in and out. the out pin connects to the anode of the internal boost diode. this pin also supplies the current to the lt3975s internal regulator when out is above 3.2v. connect this pin to the output when the programmed output voltage is less than 16v. boost (pin 4): this pin is used to provide a drive volt - age, higher than the input voltage, to the internal bipolar npn power switch. sw (pins 5, 6, 7): the sw pin is the output of an internal power switch. connect these pins to the inductor, catch diode, and boost capacitor. nc (pins 8, 9): no connects. these pins are not connected to internal circuitry. v in (pins 10, 11, 12): the v in pin supplies current to the lt3975s internal circuitry and to the internal power switch. these pins must be locally bypassed. en (pin 13): the part is in shutdown when this pin is low and active when this pin is high. the hysteretic threshold voltage is 1.08v going up and 1.02v going down. the en threshold is only accurate when v in is above 4.3v. if v in is lower than 3.9v, internal uvlo will place the part in shutdown. tie to v in if shutdown feature is not used. rt (pin 14): a resistor is tied between rt and ground to set the switching frequency. pg (pin 15): the pg pin is the open-drain output of an internal comparator. pgood remains low until the fb pin is within 8.4% of the final regulation voltage. pgood is valid when v in is above 2v. sync (pin 16): this is the external clock synchronization input. ground this pin for low ripple burst mode operation at low output loads. tie to a clock source for synchroni - zation, which will include pulse skipping at low output loads. when in pulse-skipping mode, quiescent current increases to 11a in a typical application at no load. do not float this pin. gnd (exposed pad pin 17): ground. the exposed pad must be soldered to the pcb. typical performance characteristics t a = 25c, unless otherwise noted. load transient: 0.5a to 2.5a load transient: 20ma to 2a v out 200mv/div i l 1a/div 20s/div 12v in 3.3v out c out = 47f 3975 g37 v out 200mv/div i l 1a/div 20s/div 3975 g38 12v in 3.3v out c out = 47f
lt3975 9 3975f block diagram + ? + ? + ? + ? oscillator 200khz to 2mhz burst mode detect v c clamp v c slope comp r v in v in en boost 0.5v sw shdn switch latch ss 1.8a v out c2 c3 c4 opt l1 d1 out rt r2 gnd error amp r1 fb r t c1 pg 1.097v 1.02v s q 3975 bd internal 1.197v ref sync + ? shdn + c5 + ?
lt3975 10 3975f operation the lt3975 is a constant frequency, current mode step - down regulator. an oscillator, with frequency set by rt, sets an rs flip-flop, turning on the internal power switch. an amplifier and comparator monitor the current flowing between the v in and sw pins, turning the switch off when this current reaches a level determined by the voltage at v c (see block diagram). an error amplifier measures the output voltage through an external resistor divider tied to the fb pin and servos the v c node. if the error ampli - fiers output increases, more current is delivered to the output; if it decreases, less current is delivered. an active clamp on the v c pin provides current limit. the v c pin is also clamped by the voltage on the ss pin; soft-start is implemented by generating a voltage ramp at the ss pin using an external capacitor. an internal regulator provides power to the control circuitry. the bias regulator normally draws power from the v in pin, but if the out pin is connected to an external volt - age higher than 3.2v, bias power will be drawn from the external source (typically the regulated output voltage). this improves efficiency. if the en pin is low, the lt3975 is shut down and draws 700na from the input. when the en pin falls below 1.02v, the switching regulator will shut down, and when the en pin rises above 1.08v, the switching regulator will become active. this accurate threshold allows programmable undervoltage lockout. the switch driver operates from either v in or from the boost pin. an external capacitor is used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal bipolar npn power switch for efficient operation. to further optimize efficiency, the lt3975 automatically switches to burst mode operation in light load situations. between bursts, all circuitry associated with controlling the output switch is shut down reducing the input supply current to 1.7a. in a typical application, 2.7a will be consumed from the supply when regulating with no load. the oscillator reduces the lt3975s operating frequency when the voltage at the fb pin is low. this frequency foldback helps to control the output current during start- up and overload. the lt3975 can provide up to 2.5a of output current. a current limit foldback feature throttles back the cur - rent limit during overload conditions to limit the power dissipation. when ss is below 2v, the lt3975 overrides the current limit foldback circuit to avoid interfering with start-up. thermal shutdown further protects the part from excessive power dissipation, especially in elevated ambient temperature environments. if the input voltage decreases towards the programmed output voltage, the lt3975 will start to skip switch-off times and decrease the switching frequency to maintain output regulation. as the input voltage decreases below the programmed output voltage, the output voltage will be regulated 500mv below the input voltage. this enforced minimum dropout voltage limits the duty cycle and keeps the boost capacitor charged during dropout conditions. since sufficient boost voltage is maintained, the internal switch can fully saturate yielding low dropout performance. the lt3975 contains a power good comparator which trips when the fb pin is at 91.6% of its regulated value. the pg output is an open-drain transistor that is off when the output is in regulation, allowing an external resistor to pull the pg pin high. power good is valid when v in is above 2v. when the lt3975 is shut down the pg pin is actively pulled low.
lt3975 11 3975f applications information achieving ultralow quiescent current to enhance efficiency at light loads, the lt3975 operates in low ripple burst mode operation, which keeps the out - put capacitor charged to the desired output voltage while minimizing the input quiescent current. in burst mode operation the lt3975 delivers single pulses of current to the output capacitor followed by sleep periods where the output power is supplied by the output capacitor. when in sleep mode the lt3975 consumes 1.7a, but when it turns on all the circuitry to deliver a current pulse, the lt3975 consumes several ma of input current in addition to the switch current. therefore, the total quiescent current will be greater than 1.7a when regulating. as the output load decreases, the frequency of single cur - rent pulses decreases (see figure 1) and the percentage of time the lt3975 is in sleep mode increases, resulting in much higher light load efficiency. by maximizing the time between pulses, the converter quiescent current gets closer to the 1.7a ideal. therefore, to optimize the quiescent current performance at light loads, the current in the feedback resistor divider and the reverse current in the catch diode must be minimized, as these appear to the output as load currents. use the largest possible feedback resistors and a low leakage schottky catch diode in applications utilizing the ultralow quiescent current performance of the lt3975. the feedback resistors should preferably be on the order of m and the schottky catch figure 1. switching frequency in burst mode operation diode should have less than a few a of typical reverse leakage at room temperature. these two considerations are reiterated in the fb resistor network and catch diode selection sections. it is important to note that another way to decrease the pulse frequency is to increase the magnitude of each single current pulse. however, this increases the output voltage ripple because each cycle delivers more power to the output capacitor. the magnitude of the current pulses was selected to ensure less than 15mv of output ripple in a typical application. see figure 2. figure 2. burst mode operation while in burst mode operation, the burst frequency and the charge delivered with each pulse will not change with output capacitance. therefore, the output voltage ripple will be inversely proportional to the output capacitance. in a typical application with a 22f output capacitor, the output ripple is about 10mv, and with a 47f output capacitor the output ripple is about 5mv. the output voltage ripple can continue to be decreased by increasing the output capacitance, though care must be taken to minimize the effects of output capacitor esr and esl. at higher output loads (above 150ma for the front page application) the lt3975 will be running at the frequency programmed by the r t resistor, and will be operating in standard pwm mode. the transition between pwm and low ripple burst mode operation is seamless, and will not disturb the output voltage. to ensure proper burst mode operation, the sync pin must be grounded. when synchronized with an external clock, the lt3975 will pulse skip at light loads. at very load current (ma) 0 switching frequency (khz) 500 600 700 160 3975 f01 400 300 0 40 80 120 20 60 100 140 200 100 900 800 v out = 5v f sw = 800khz v out = 3.3v f sw = 600khz v sw 5v/div v out 10mv/div i l 0.5a/div 5s/div v in = 12v v out = 3.3v i load = 20ma c out = 47f 3975 f02
lt3975 12 3975f applications information light loads, the part will go to sleep between groups of pulses, so the quiescent current of the part will still be low, but not as low as in burst mode operation. the quiescent current in a typical application when synchronized with an external clock is 11a at no load. holding the sync pin dc high yields no advantages in terms of output ripple or minimum load to full frequency, so is not recommended. fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistor values according to: r1 = r2 v out 1.197v ? 1 ? ? ? ? ? ? reference designators refer to the block diagram. 1% resistors are recommended to maintain output voltage accuracy. the total resistance of the fb resistor divider should be selected to be as large as possible to enhance low current performance. the resistor divider generates a small load on the output, which should be minimized to optimize the low supply current at light loads. when using large fb resistors, a 10pf phase lead capacitor should be connected from v out to fb. setting the switching frequency the lt3975 uses a constant frequency pwm architecture that can be programmed to switch from 200khz to 2mhz by using a resistor tied from the rt pin to ground. a table showing the necessary r t value for a desired switching frequency is in table 1. to estimate the necessary r t value for a desired switching frequency, use the equation: r t = 51.1 f sw ( ) 1.09 ? 9.27 where r t is in k and f sw is in mhz. table 1. switching frequency vs r t value switching frequency (mhz) r t value (k) 0.2 294 0.3 182 0.4 130 0.6 78.7 0.8 54.9 1.0 41.2 1.2 32.4 1.4 26.1 1.6 21.5 1.8 17.8 2.0 14.7 2.2 12.4 operating frequency trade-offs selection of the operating frequency is a trade-off between efficiency, component size, minimum dropout voltage, and maximum input voltage. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disadvantages are lower efficiency, and lower maximum input voltage. the highest acceptable switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out + v d t on(min) v in ? v sw + v d ( ) where v in is the typical input voltage, v out is the output voltage, v d is the catch diode drop (~0.5v), and v sw is the internal switch drop (~0.22v at max load). this equa - tion shows that slower switching frequency is necessary to safely accommodate high v in /v out ratio. this is due to the limitation on the lt3975s minimum on-time. the minimum on-time is a strong function of temperature. use the typical minimum on-time curve to design for an applications maximum temperature, while adding about 30% for part-to-part variation. the minimum duty cycle that can be achieved taking minimum on time into account is: dc min = f sw ? t on(min) where f sw is the switching frequency, the t on(min) is the minimum switch on-time.
lt3975 13 3975f applications information a good choice of switching frequency should allow ad - equate input voltage range (see next two sections) and keep the inductor and capacitor values small. maximum input voltage range the lt3975 can operate from input voltages of up to 42v. often the highest allowed v in during normal operation (v in(op-max) ) is limited by the minimum duty cycle rather than the absolute maximum ratings of the v in pin. it can be calculated using the following equation: v in(op-max) = v out + v d f sw ? t on(min) ? v d + v sw where t on(min) is the minimum switch on-time. a lower switching frequency can be used to extend normal opera - tion to higher input voltages. the circuit will tolerate inputs above the maximum op - erating input voltage and up to the absolute maximum ratings of the v in and boost pins, regardless of chosen switching frequency. however, during such transients where v in is higher than v in(op-max) , the lt3975 will enter pulse-skipping operation where some switching pulses are skipped to maintain output regulation. the output voltage ripple and inductor current ripple will be higher than in typical operation. do not overload when v in is greater than v in(op-max) . minimum input voltage range the minimum input voltage is determined by either the lt3975s minimum operating voltage of 4.3v, its maximum duty cycle, or the enforced minimum dropout voltage. see the typical performance characteristics section for the minimum input voltage across load for outputs of 3.3v and 5v. the duty cycle is the fraction of time that the internal switch is on during a clock cycle. unlike many fixed fre - quency regulators, the lt3975 can extend its duty cycle by remaining on for multiple clock cycles. the lt3975 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (c3 in the block diagram). eventually, the voltage on the boost capacitor falls and requires refreshing. when this occurs, the switch will turn off, allowing the inductor current to recharge the boost capacitor. this places a limitation on the maximum duty cycle as follows: dc max = sw sw + 1 where sw is equal to the beta of the internal power switch. the beta of the power switch is typically about 50, which leads to a dc max of about 98%. this leads to a minimum input voltage of approximately: v in(min1) = v out + v d dc max ? v d + v sw where v out is the output voltage, v d is the catch diode drop, v sw is the internal switch drop and dc max is the maximum duty cycle. the final factor affecting the minimum input voltage is the minimum dropout voltage. when the out pin is tied to the output, the lt3975 regulates the output such that it stays 500mv below v in . this enforced minimum drop - out voltage is due to reasons that are covered in the next section. this places a limitation on the minimum input voltage as follows: v in(min2) = v out + v dropout(min) where v out is the programmed output voltage and v dropout(min) is the minimum dropout voltage of 500mv. combining these factors leads to the overall minimum input voltage: v in(min) = max (v in(min1) , v in(min2) , 4.3v) minimum dropout voltage to achieve a low dropout voltage, the internal power switch must always be able to fully saturate. this means that the boost capacitor, which provides a base drive higher than v in , must always be able to charge up when the part starts up and then must also stay charged during all operating conditions.
lt3975 14 3975f applications information during start-up if there is insufficient inductor current, such as during light load situations, the boost capacitor will be unable to charge. when the lt3975 detects that the boost capacitor is not charged, it activates a 100ma (typical) pull-down on the out pin. if the out pin is connected to the output, the extra load will increase the inductor current enough to sufficiently charge the boost capacitor. when the boost capacitor is charged, the current source turns off, and the part may re-enter burst mode operation. to keep the boost capacitor charged regardless of load during dropout conditions, a minimum dropout voltage is enforced. when the out pin is tied to the output, the lt3975 regulates the output such that: v in C v out > v dropout(min) where v dropout(min) is 500mv. the 500mv dropout volt - age limits the duty cycle and forces the switch to turn off regularly to charge the boost capacitor. since sufficient voltage across the boost capacitor is maintained, the switch is allowed to fully saturate and the internal switch drop stays low for good dropout performance. figure 3 shows the overall v in to v out performances during start-up and dropout conditions. measured dropout voltage, can be significantly reduced. additionally, when operating in dropout at high currents, high ripple voltage on the input and output can generate audible noise. this noise can also be significantly reduced by adding bulk capacitance to the input and output to reduce the voltage ripple. inductor selection and maximum output current for a given input and output voltage, the inductor value and switching frequency will determine the ripple current. the ripple current increases with higher v in or v out and decreases with higher inductance and faster switching frequency. a good first choice for the inductor value is: l = v out + v d 1.5 ? f sw where f sw is the switching frequency in mhz, v out is the output voltage, v d is the catch diode drop (~0.5v) and l is the inductor value is h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be about 30% higher. for robust operation in fault conditions (start-up or overload) and high input voltage (>30v), the saturation current should be above 8.5a. to keep the efficiency high, the series resistance (dcr) should be less than 0.1, and the core material should be intended for high frequency applications. table 2 lists several inductor vendors. table 2. inductor vendors vendor url coilcraft www.coilcraft.com sumida www.sumida.com toko www.tokoam.com wrth elektronik www.we-online.com coiltronics www.cooperet.com murata www.murata.com the inductor value must be sufficient to supply the desired maximum output current (i out(max) ), which is a function of the switch current limit (i lim ) and the ripple current. i out(max) = i lim ? ? i l 2 figure 3. v in to v out performance v in 1v/div v out 1v/div v out v in 100ms/div 1k load (5ma in regulation) 3975 f03 it is important to note that the 500mv dropout voltage specified is the minimum difference between v in and v out . when measuring v in to v out with a multimeter, the measured value will be higher than 500mv because you have to add half the ripple voltage on the input and half the ripple voltage on the output. with the normal ceramic capacitors specified in the data sheet, this mea- sured dropout voltage can be as high as 650mv at high load. if some bulk electrolytic capacitance is added to the input and output the voltage ripple, and subsequently the
lt3975 15 3975f applications information the lt3975 limits its peak switch current in order to protect itself and the system from overload and short-circuit faults. the lt3975s switch current limit (i lim ) is typically 5.4a at low duty cycles and decreases linearly to 4.4a at dc = 0.8. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: ? i l = 1?dc ( ) ? v out + v d ( ) l ? f sw where f sw is the switching frequency of the lt3975, dc is the duty cycle and l is the value of the inductor. therefore, the maximum output current that the lt3975 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. the inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current (i out(max) ) given the switching frequency, and maximum input voltage used in the desired application. the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a higher maximum load current and reduces the output voltage ripple. if your load is lower than the maximum load current, than you can relax the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on the input voltage. in addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. for details of maximum output current and discontinuous operation, see linear technologys application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid sub-harmonic oscillations, see application note 19. one approach to choosing the inductor is to start with the simple rule given above, look at the available induc - tors, and choose one to meet cost or space goals. then use the equations above to check that the lt3975 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than i l /2. current limit foldback and thermal protection the lt3975 has a large peak current limit to ensure a 2.5a max output current across duty cycle and current limit distribution, as well as allowing a reasonable inductor ripple current. during a short-circuit fault, having a large current limit can lead to excessive power dissipation and temperature rise in the lt3975, as well as the inductor and catch diode. to limit this power dissipation, the lt3975 starts to fold back the current limit when the fb pin falls below 0.8v. the lt3975 typically lowers the peak current limit about 40% from 5.4a to 3.3a. during start-up, when the output voltage and fb pin are low, current limit foldback could hinder the lt3975s ability to start up into a large load. to avoid this potential problem, the lt3975s current limit foldback will be disabled until the ss pin has charged above 2v. therefore, the use of a soft-start capacitor will keep the current limit foldback feature out of the way while the lt3975 is starting up. the lt3975 has thermal shutdown to further protect the part during periods of high power dissipation, particularly in high ambient temperature environments. the thermal shutdown feature detects when the lt3975 is too hot and shuts the part down, preventing switching. when the thermal event passes and the lt3975 cools, the part will restart and resume switching. a thermal shutdown event actively discharges the soft-start capacitor. input capacitor bypass the input of the lt3975 circuit with a ceramic capaci - tor of x7r or x5r type. y5v types have poor performance over temperature and applied voltage, and should not be used. a 4.7f to 10f ceramic capacitor is adequate to bypass the lt3975 and will easily handle the ripple cur - rent. note that larger input capacitance is required when a lower switching frequency is used (due to longer on times). if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a low performance electrolytic capacitor.
lt3975 16 3975f step-down regulators draw current from the input sup - ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3975 and to force this very high frequency switching current into a tight local loop, minimizing emi. a 4.7f capacitor is capable of this task, but only if it is placed close to the lt3975 (see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3975. a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. if the lt3975 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, pos - sibly exceeding the lt3975s voltage rating. if the input supply is poorly controlled or the user will be plugging the lt3975 into an energized supply, the input network should be designed to prevent this overshoot. see linear technology application note 88 for a complete discussion. output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the lt3975 to produce the dc output. in this role it determines the output ripple, so low impedance (at the switching frequency) is important. the second function is to store energy in order to satisfy transient loads and stabilize the lt3975s control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good starting value is: c out = 200 v out ? f sw where f sw is in mhz, and c out is the recommended output capacitance in f. use x5r or x7r types. this choice will provide low output ripple and good transient response. transient performance can be improved with a higher value capacitor if combined with a phase lead capacitor (typically 10pf) between the output and the feedback pin. a lower value of output capacitor can be used to save space and cost but transient performance will suffer. when choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). a physically larger capacitor or one with a higher voltage rating may be required. table 3 lists several capacitor vendors. table 3. recommended ceramic capacitor vendors manufacturer url avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com ceramic capacitors when in dropout, the lt3975 can excite ceramic ca - pacitors at audio frequencies. at high load, this could be unacceptable. simply adding bulk input capacitance to the input and output will significantly reduce the voltage ripple and the audible noise generated at these nodes to acceptable levels. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the lt3975. as pre - viously mentioned, a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. if the lt3975 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt3975s rating. if the input supply is poorly controlled or the user will be plugging the lt3975 into an energized supply, the input network should be designed to prevent this overshoot. see linear technology application note 88 for a complete discussion. catch diode selection the catch diode (d1 from the block diagram) conducts current only during the switch off time. average forward current in normal operation can be calculated from: i d(avg) = i out v in ? v out v in ? ? ? ? ? ? where i out is the output load current. the current rating of the diode should be selected to be greater than or equal to the applications output load current, so that the diode is applications information
lt3975 17 3975f robust for a wide input voltage range. a diode with even higher current rating can be selected for the worst-case scenario of overload, where the max diode current can then increase to the typical peak switch current. short circuit is not the worst-case condition due to current limit foldback. peak reverse voltage is equal to the regulator input voltage. for inputs up to 40v, a 40v diode is adequate. an additional consideration is reverse leakage current. when the catch diode is reversed biased, any leakage current will appear as load current. when operating under light load conditions, the low supply current consumed by the lt3975 will be optimized by using a catch diode with minimum reverse leakage current. low leakage schottky diodes often have larger forward voltage drops at a given current, so a trade-off can exist between low load and high load efficiency. often schottky diodes with larger reverse bias ratings will have less leakage at a given output voltage than a diode with a smaller reverse bias rating. therefore, superior leakage performance can be achieved at the expense of diode size. table 4 lists several schottky diodes and their manufacturers. boost and out pin considerations capacitor c3 and the internal boost schottky diode (see the block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.47f capacitor will work well. the boost pin must be more than 1.8v above the sw pin for best efficiency and more than 2.6v above the sw pin to allow the lt3975 to skip off times to achieve very high duty cycles. for outputs between 3.2v and 16v, the standard circuit with the out pin connected to the output (figure 4a) is best. below 3.2v the internal schottky diode may not be able to sufficiently charge the boost capacitor. above 16v, the out pin abs max is violated. for outputs between 2.5v and 3.2v, an external schottky diode to the output is sufficient because an external schottky will have much lower forward voltage drop than the internal boost diode. applications information table 4. schottky diodes. the reverse current values listed are estimates based off of typical curves for reverse current vs reverse voltage at 25c part number v r (v) i ave (a) v f at 3a typ 25c (mv) v f at 3a max 25c (mv) i r at v r = 20v 25c (a) on semiconductor mbra340t3 40 3 410 450 10 mbrs340t3 40 3 410 500 10 mbrd340 40 3 450 600 4 diodes inc. b340a 40 3 485 500 2 b340la 40 3 400 450 100 b360a 60 3 600 700 50 pds340 40 3 450 490 4 pds360 60 3 570 620 0.45 sbr3u40p1 40 3 420 470 40 sbr3u30p1 30 3 390 430 100 sbr3m30p1 30 3 460 500 12 sbr3u60p1 60 3 580 650 1.7 DFLS240l 40 2 500 4 DFLS240 40 2 700 1 for output voltages less than 2.5v, there are two options. an external schottky diode can charge the boost capaci - tor from the input (figure 4c) or from an external voltage source (figure 4d). using an external voltage source is the better option because it is more efficient than charging the boost capacitor from the input. however, such a voltage rail is not always available in all systems. for output volt - ages greater than 16v, an external schottky diode from an external voltage source should be used to charge the boost capacitor (figure 4e). in applications using an ex - ternal voltage source, the supply should be between 3.1v and 16v. when using the input, the input voltage may not exceed 27v. in all cases, the maximum voltage rating of the boost pin must not be exceeded.
lt3975 18 3975f applications information figure 5. the minimum input voltage depends on output voltage and load current boost lt3975 (4a) for 3.2v v out 16v gnd v in v in sw out v out boost lt3975 (4d) for v out < 2.5v, 3.1v v s 16v gnd v in v in sw out v out v s boost lt3975 (4e) for v out > 16v, 3.1v v s 16v gnd v in v in sw out v out 3875 f04 v s boost lt3975 (4c) for v out < 2.5v, v in < 27v gnd v in v in sw out v out boost lt3975 (4b) for 2.5v v out 3.2v gnd v in v in sw out v out figure 4. five circuits for generating the boost voltage load current (a) 0 input voltage (v) 5.5 6.0 6.5 2 3975 f05a 5.0 4.5 4.0 0.5 1 1.5 2.5 v out = 5v f sw = 800khz to run/to start load current (a) 0 input voltage (v) 4.0 4.5 5.0 2 3975 f05b 3.5 3.0 2.5 0.5 1 1.5 2.5 v out = 3.3v front page application to run/to start when the output is above 16v, the out pin can not be tied to the output or the out pin abs max will be violated. it should instead be tied to gnd (figure 4e). this is to pre- vent the dropout circuitry from interfering with switching behavior and to prevent the 100ma active pull-down from drawing power. it is important to note that when the output is above 16v and the out pin is grounded, the dropout circuitry is not connected, so the minimum dropout will be about 1.5v, rather than 500mv. if the output is less than 3.2v and an external schottky is used to charge the boost capacitor, the out pin should still be tied to the output even though the minimum input voltage of the lt3975 will be limited by the 4.3v minimum rather than the minimum dropout voltage. with the out pin connected to the output, a 100ma ac - tive load will charge the boost capacitor during light load start-up and an enforced 500mv minimum dropout voltage will keep the boost capacitor charged across operating conditions (see minimum dropout voltage section). this yields excellent start-up and dropout performance. figure 5 shows the minimum input voltage for 3.3v and 5v outputs.
lt3975 19 3975f enable and undervoltage lockout the lt3975 is in shutdown when the en pin is low and active when the pin is high. the falling threshold of the en comparator is 1.02v, with 60mv of hysteresis. the en pin can be tied to v in if the shutdown feature is not used. undervoltage lockout (uvlo) can be added to the lt3975 as shown in figure 6. typically, uvlo is used in situa - tions where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source cur - rent increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where the problems might occur. the uvlo threshold can be adjusted by setting the values r3 and r4 such that they satisfy the following equation: v uvlo = v en(thresh) r3 + r4 r4 ? ? ? ? ? ? where v en(thresh) is the falling threshold of the en pin, which is approximately 1.02v, and where switching should stop when v in falls below v uvlo . note that due to the comparators hysteresis, switching will not start until the input is about 6% above v uvlo . when operating in burst mode operation for light load currents, the current through the uvlo resistor network can easily be greater than the supply current consumed by the lt3975. therefore, the uvlo resistors should be large to minimize their effect on efficiency at low loads. capacitor generating a voltage ramp on the ss pin. the ss pin clamps the internal v c node, which slowly ramps up the current limit. maximum current limit is reached when the ss pin is about 1.5v or higher. by selecting a large enough capacitor, the output can reach regulation without overshoot. figure 7 shows start-up waveforms for a typical application with a 10nf capacitor on ss for a 1.65 load when the en pin is pulsed high for 7ms. the external ss capacitor is actively discharged when the en pin is low, or during thermal shutdown. the active pull-down on the ss pin has a resistance of about 150. applications information shdn 1.02v en lt3975 v in r3 r4 lt3975 f06 + ? figure 6. undervoltage lockout figure 7. soft-start waveforms for the front-page application with a 10nf capacitor on ss. en is pulsed high for about 7ms with a 1.65 load resistor v out 1v/div v ss 0.5v/div i l 1a/div 1ms/div 3975 f07 soft-start the ss pin can be used to soft start the lt3975 by throt - tling the maximum input current during start-up and reset. an internal 1.8a current source charges an external synchronization to select low ripple burst mode operation, tie the sync pin below 0.5v (this can be ground or a logic output). synchronizing the lt3975 oscillator to an external fre - quency can be done by connecting a square wave (with 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have valleys that are below 0.5v and peaks above 1.5v (up to 6v). the lt3975 will pulse skip at low output loads while syn - chronized to an external clock to maintain regulation. at very light loads, the part will go to sleep between groups of pulses, so the quiescent current of the part will still be low, but not as low as in burst mode operation. the quiescent current in a typical application when synchronized with an external clock is 11a at no load. holding the sync pin dc high yields no advantages in terms of output ripple or minimum load to full frequency, so is not recommended. never float the sync pin.
lt3975 20 3975f the lt3975 may be synchronized over a 250khz to 2mhz range. the r t resistor should be chosen to set the lt3975 switching frequency 20% below the lowest synchronization input. for example, if the synchronization signal will be 250khz and higher, the r t should be selected for 200khz. to assure reliable and safe operation the lt3975 will only synchronize when the output voltage is near regulation as indicated by the pg flag. it is therefore necessary to choose a large enough inductor value to supply the required output current at the frequency set by the r t resistor (see inductor selection section). the slope compensation is set by the r t value, while the minimum slope compensation required to avoid subharmonic oscillations is established by the inductor size, input voltage and output voltage. since the synchronization frequency will not change the slopes of the inductor current waveform, if the inductor is large enough to avoid subharmonic oscillations at the frequency set by r t , than the slope compensation will be sufficient for all synchronization frequencies. power good flag the pg pin is an open-drain output which is used to indicate to the user when the output voltage is within regulation. when the output is lower than the regulation voltage by more than 8.4%, as determined from the fb pin voltage, the pg pin will pull low to indicate the power is not good. otherwise, the pg pin will go high impedance and can be pulled logic high with a resistor pull-up. the pg pin is only comparing the output voltage to an accurate refer - ence when the lt3975 is enabled and v in is above 4.3v. when the part is shutdown, the pg is actively pulled low to indicate that the lt3975 is not regulating the output. the input voltage must be greater than 1.4v to fully turn-on the active pull-down device. figure 8 shows the status of the pg pin as the input voltage is increased. shorted and reversed input protection if the inductor is chosen so that it wont saturate excessively, a lt3975 buck regulator will tolerate a shorted output and the power dissipation will be limited by current limit fold - back (see current limit foldback and thermal protection section). there is another situation to consider in systems where the output will be held high when the input to the applications information figure 8. pg pin voltage versus input voltage when pg is connected to 3v through a 150k resistor. the fb pin voltage is 1.15v input voltage (v) 0 pg pin voltage (v) 2 3 4 3975 f08 1 0 1 2 2.5 5 4 3 0.5 1.5 4.5 3.5 lt3975 is absent. this may occur in battery charging ap - plications or in battery backup systems where a battery or some other supply is diode ored with the lt3975s output. if the v in pin is allowed to float and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the lt3975s internal circuitry will pull its quiescent current through its sw pin. this is fine if your system can tolerate a few a in this state. if you ground the en pin, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, regardless of en, parasitic diodes inside the lt3975 can pull current from the output through the sw pin and the v in pin. figure 9 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 10 shows a sample component placement with trace, ground plane and via locations, which serves as a good pcb layout example. note that large, switched currents flow in the lt3975s v in and sw pins, the catch diode (d1), and the input capacitor (c1). the loop formed by these compo- nents should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local,
lt3975 21 3975f high temperature considerations for higher ambient temperatures, care should be taken in the layout of the pcb to ensure good heat sinking of the lt3975. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these layers will spread the heat dissipated by the lt3975. placing additional vias can reduce the thermal resistance further. when operating at high ambient temperatures, the maximum load current should be derated as the ambient temperature approaches the maximum junction rating. power dissipation within the lt3975 can be estimated by calculating the total power loss from an efficiency measure - ment and subtracting the catch diode loss and inductor loss. the die temperature is calculated by multiplying the lt3975 power dissipation by the thermal resistance from junction to ambient. also keep in mind that the leakage current of the power schottky diode goes up exponentially with junction tem - perature. when the power switch is off, the power schottky diode is in parallel with the power converters output filter stage. as a result, an increase in a diodes leakage current results in an effective increase in the load, and a corresponding increase in the input quiescent current. therefore, the catch schottky diode must be selected with care to avoid excessive increase in light load supply current at high temperatures. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. applications information v in boost v in en 3975 f09 v out backup lt3975 d4 b360a sw out gnd fb + figure 9. diode d4 prevents a shorted input from discharging a backup battery tied to the output. it also protects the circuit from a reversed input. the lt3975 runs only when the input is present figure 10. layout showing a good pcb design v out v in 3975 f10 v out rt pg fb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? out sw en bst 17 ss sync unbroken ground plane below these components. the sw and boost nodes should be as small as possible. finally, keep the fb and rt nodes small so that the ground traces will shield it from the sw and boost nodes. the exposed pad on the bottom of the package must be soldered to ground so that the pad acts as a heat sink. to keep thermal resistance low, extend the ground plane as much as pos - sible, and add thermal vias under and near the lt3975 to additional ground planes within the circuit board and on the bottom side.
lt3975 22 3975f typical applications 5v step-down converter 4v step-down converter with a high impedance input source 12v step-down converter 2.5v step-down converter 5v, 2mhz step-down converter with power good 1.8v step-down converter v in en boost off on v in 5.7v to 42v pg 0.47f pds360 47f 1210 3975 ta02 10nf 10f 316k f = 800khz l = ihlp-2020cz-01 54.9k v out 5v 2.5a 4.7h lt3975 ss rt sw out fb sync gnd 1m 10pf v in en boost off on v in 12.9v to 42v pg 0.47f pds360 22f 1210 2 3975 ta03 10nf 10f 110k f = 800khz l = ihlp-3232cz-01 54.9k v out 12v 2.5a 10h lt3975 ss rt sw out fb sync gnd 1m 10pf v in en boost off on v in 5.9v to 18v (42v transients) 0.47f pds360 22f 1210 3975 ta04 10nf 4.7f 316k 150k f = 2mhz l = ihlp-2525cz-01 14.7k v out 5v 2.5a pgood 2.2h lt3975 ss rt sw out pg fb sync gnd 1m 10pf v in pg boost en 0.47f pds360 47f 1210 3975 ta05 47nf c bulk 100f 24v 10f 432k f = 800khz l = ihlp-2525ez-01 54.9k 499k 5.49m v out 4v 2.5a 4.7h lt3975 ss rt sw out fb sync gnd 1m 10pf + v + ? v in en boost off on v in 4.3v to 42v pg 0.47f pds360 100f 1210 3975 ta06 10nf 10f 909k f = 400khz l = ihlp-2525ez-01 130k v out 2.5v 2.5a 6.8h dfls160 lt3975 ss rt sw out fb sync gnd 1m 10pf v in en boost off on v in 4.3v to 27v pg 0.47f pds360 100f 1210 3975 ta07 10nf 10f 1m f = 500khz l = ihlp-2020cz-01 97.6k v out 1.8v 2.5a 3.3h dfls160 lt3975 ss rt sw out fb sync gnd 499k 10pf
lt3975 23 3975f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0911 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e)
lt3975 24 3975f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0812 ? printed in usa related parts typical application 1.2v step-down converter v in en boost off on v in 4.3v to 27v (42v transient) pg 0.47f pds360 3.3v 100f 1210 3975 ta08 10nf 10f f = 400khz l = ihlp-2525ez-01 130k v out 1.2v 2.5a 4.7h dfls160 lt3975 ss rt sw out fb sync gnd part number description comments lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode ? operation v in = 3.6v to 38v, transients to 60v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in = 3.6v to 58v, transients to 80v, v out(min) = 0.79v, i q = 75a, i sd < 1a, 3mm w 4mm dfn-16, msop-16e lt3971 38v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in = 4.2v to 38v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3991 55v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in = 4.2v to 55v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3970 40v, 350ma (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.5a of quiescent current v in = 4.2v to 40v, v out(min) = 1.2v, i q = 2.5a, i sd < 0.7a, 2mm w 3mm dfn-10, msop-10e lt3990 62v, 350ma (i out ), 2.2mhz, high efficiency step-down dc/dc converter with only 2.5a of quiescent current v in = 4.2v to 62v, v out(min) = 1.2v, i q = 2.5a, i sd < 0.7a, 3mm w 3mm dfn-10, msop-16e

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